The present invention relates to a semiconductor device and a process of manufacture thereof; and, more particularly, the invention relates to a technique that is effective in producing a highly integrated circuit device that has a high performance and a high reliability.
With a tendency to enhance the performance and increase the degree of miniaturization of a semiconductor device, a self alignment technique that is capable of absorbing mask alignment errors has been employed frequently.
For example, Japanese Patent Application Laid-Open No. Hei 11(1999)-26714 discloses a technique which calls for covering, with a silicon nitride film, gate electrodes of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting the memory cell of a DRAM, forming an interlayer insulating film made of a silicon oxide film, and then forming a plug for connecting source and drain regions of the MISFET. In the processing step of providing a connecting hole wherein this plug is to be formed, etching is carried out in two sub-steps, that is, a first etching sub-step permitting etching of the silicon oxide film, but not permitting easy etching of the silicon nitride film, and a second etching sub-step permitting etching of the silicon nitride film. Since the MISFET (selecting MISFET) of the DRAM memory cell is processed with a minimum processing size, mask misregistration between a gate electrode pattern and a connecting hole pattern cannot be avoided upon formation of the connecting hole between the gate electrodes, and accurate processing of the connecting hole cannot be attained without using a self alignment technique. In the technique as disclosed in the above-described literature, the silicon nitride film covering the gate electrodes serves as an etching stopper, whereby the connecting hole can be processed in self alignment with the gate electrode.
According to the above-described technique, the silicon oxide film is formed so as to be thinner than the silicon oxide film serving as an interlayer insulating film, and the silicon nitride film serves as an etching stopper so that sufficient overetching can be conducted in the above-described first etching sub-step. Even a minute connecting hole, or a connecting hole having a great aspect ratio, can be formed with a uniform thickness on the wafer, and, in addition, the process margin can be increased. In the second etching sub-step, owing to a sufficiently small thickness of the silicon nitride film serving as a stopper, excessive etching of a substrate can be inhibited even if sufficient over-etching is conducted. In short, a connecting hole can be formed in self alignment with the surface of the substrate. In particular, when the bottom portion of the connecting hole overlaps with an element isolation region, there is a possibility of the silicon oxide film, which constitutes the element isolation region, being etched excessively. By adoption of a two-stage etching process, excessive etching of the element isolation region can be controlled within a sufficiently acceptable range. As a result, leakage current of the MISFET due to excessive etching of the substrate (element isolation region) can be inhibited, whereby, in the case of a DRAM, the refresh properties can be improved.
The above-described self alignment processing relative to the substrate surface can be applied, for example, to a wiring step using a damascene process. More specifically, upon defining a wiring trench for metallization or a connecting hole in an interlayer insulating film, a thin silicon nitride film is formed in advance at a position corresponding to the bottom portion of the wiring trench or bottom portion of the connecting hole, and then, the wiring trench or connecting hole is formed in a manner similar to the above-described two-stage etching step. In such a step, it is possible to inhibit excessive etching of a member at the bottom portion of the wiring trench or connecting hole, improve the uniformity of the depth of the wiring trench or connecting hole, and to actualize definite connection between wiring layers.
There are a variety of film formation methods for formation of a silicon nitride film, for example, the thermal CVD (Chemical Vapor Deposition) and plasma CVD. For example, Japanese Patent Application Laid-Open No. Hei 2(1990)-224430 discloses a technique for using, as an interlayer insulating film or passivation film, a silicon nitride film formed by the ECR (Electron Cyclotron Resonance)-CVD using a raw material gas having silane (SiH4) and nitrogen (N2). Japanese Patent Application Laid-Open No. Sho 63(1988)-132434 discloses a technique for using, as a passivation film, a silicon nitride film formed by the ECR-CVD using a raw material gas having silane (SiH4) and nitrogen (N2).
The present inventors, however, have recognized that the above-described techniques involve problems. Recognition on the problems which will be described below was obtained by tests and investigation only by the present inventors, and it has not been published.
With a tendency toward miniaturization and improvement in the performance of a semiconductor device, heat treatment has been severely controlled. For miniaturization of a semiconductor device, precise control of the position and depth of a diffusion layer (impurity semiconductor region) is necessary. A high-temperature process subsequent to the precisely-controlled formation of a diffusion layer is not preferred, because it causes diffusion of impurities, thereby causing fluctuations in the position of the diffusion layer. A precise control of an impurity concentration in the diffusion layer is also desired so that re-diffusion of the impurities in the diffusion layer presumably causing fluctuations in the impurity concentration is not preferred. For improvement in the performance of a semiconductor device, it is desired to form a silicide layer over the surface of an impurity diffusion layer or over the surface of a gate electrode. Interposition of a high temperature process after the formation of a silicide layer causes various problems due to poor heat resistance of the silicide layer, for example, a change in the composition of the silicide layer owing to the re-reaction between the silicide layer and silicon layer, a lowering in conductivity of the silicide layer owing to this compositional change, an increase in the stress in the silicide layer and appearance of voids.
It is therefore impossible to form a silicon nitride film for self alignment as a film which covers the gate electrode, or a silicon nitride film for forming a wiring trench or connecting hole of a damascene process in self alignment, by using thermal CVD process, a film formation method which operates at high temperatures (usually, 700° C. or greater). According to the recognition of the present inventors, formation of a silicon nitride film by thermal CVD is accompanied with another problem in that active hydrogen (H) being generated during film formation is diffused in a diffusion layer or channel region of the MISFET, thereby causing the threshold voltage (Vth) to fluctuate.
Formation of a silicon nitride film using plasma CVD, which permits processing at low temperatures (usually about 400° C.), therefore investigated by the present inventors.
A silicon nitride film formed by plasma CVD however has a disturbance which may deteriorate the device characteristics. The disturbance is that a surface on which the silicon nitride film is to be formed receives plasma-induced damage by radicals generated in a plasma process or ion bombardment. This leads to inactivation of an impurity (boron (B), phosphorus (P), etc.) in a polycrystalline silicon film (gate electrode) on which the silicon nitride film is to be formed or in a diffusion layer (semiconductor substrate), or an increase of dangling bonds in the polycrystalline silicon film or diffusion layer, causing an increase in their resistance.
Upon formation of a silicon nitride film by plasma CVD, silane (SiH4), ammonia (NH3) and nitrogen (N2) are used as raw material gases because they afford good step coverage, but a plasma CVD film (silicon nitride film) formed using such an SiH4/NH3/N2 gas as a raw material contains much hydrogen (H). During the subsequent heat treatment, hydrogen is released from the film, causing an increase in the stress of the film (silicon nitride film). An increase in the stress of the film is a cause of deterioration of the device characteristics. A marked increase causes peeling of the film and may cause device failure.
Hydrogen thus released is diffused in a polycrystalline silicon film serving as a gate electrode or diffusion layers (source_drain) of a semiconductor substrate and becomes a cause for inactivating impurities in the polycrystalline silicon film or diffusion layers, resulting in an increase in the resistance of the gate electrode or source drain.
The hydrogen thus released and diffused in the polycrystalline silicon film or diffusion layers facilitates movement of impurities (particularly, boron (B)) in the polycrystalline film or diffusion layers and facilitates diffusion of impurities (particularly, boron) in the channel region of the MISFET. This effect causes fluctuations in the threshold voltage (Vth) of the MISFET, thereby deteriorating the performance of the semiconductor device.
As described above, in a silicon nitride film formed at low temperature, much hydrogen contained in the film is presumed to deteriorate device characteristics. Even if a silicon nitride film formed using SiH4/NH3/N2 as a raw material gas contains much hydrogen in a deposited state, this drawback can be presumed to be overcome by a method of subjecting the resulting film to thermal treatment to release hydrogen from the film, thereby reducing its hydrogen content. But this method causes peeling of a film after thermal treatment and generates foreign matter. In addition, when a contact hole is formed in a portion of film that is just peeling, coverage failure of a connecting member occurs, thereby causing a conduction failure of the contact portion.
An object of the present invention is to provide a technique that is capable of forming a silicon nitride film for self alignment at low temperatures while reducing the hydrogen content.
Another object of the present invention is to provide a film formation method that is capable of reducing plasma-induced damage upon formation of a silicon nitride film.
A further object of the present invention is to provide a semiconductor device with less fluctuations in the resistance of a polycrystalline silicon film and with less fluctuations in the threshold voltage of the MISFET.
A still further object of the present invention is to provide a semiconductor device having high performance and high reliability.
The above-described and other objects and novel features of the present invention will be apparent from the description herein and the accompanying drawings.